In nanometer CMOS technologies such as 28 nm, the maximum tolerable voltage limit for thick-oxide devices is 1.98V. However, there are number of peripheral devices which are still operating at voltages which are higher than the nominal operating voltage of the devices, for example up to 3.6V. Therefore, the need arises to design the receiver by using low voltage devices which can receive the signal up to 3.6V from external peripheral devices and down convert it to the nominal operating voltage range of the devices. Since the external input signal to the receiver is noisy, a Schmitt trigger circuit may be needed to stop noise of the signal from propagating inside the receiver.
For 3.3V receivers there are two kinds of industry standards (e.g. JEDEC Solid State Technology Association) available for the receiver. The TTL standard includes: Logic Low (VIL)≦0.8V; and Logic High (VIH)≧2.0V. The CMOS standard includes: Logic Low (VIL)≦0.35*VDDE; and Logic High (VIH)≧0.65*VDDE.
Applications include the TTL standard being followed for 3.3V receivers whereas there are also many applications where the CMOS standard is being followed. However, the conventional 3.3V CMOS receiver architecture available includes the following constraints: there is active power consumption from PAD during the transition which can lead to operational failures; and the conventional architecture of 3.3V receivers designed by using 1.8V devices cannot support the CMOS standard if the threshold voltage of the CMOS devices used for Schmitt design are of the order of 0.5V and higher.